3.2.1.4 ICs

  1. Pin names shall be shown for all ICs unless indicated by symbolic representation such as simple logic gates.
  2. Pins shall have their ‘Electrical Type’ defined as shown in the datasheet.
  3. Complex IC symbols such as processors and FPGAs shall have pin-outs as defined in the datasheet.
  4. Interface ICs shall have their IO logically arranged to simplify connectivity e.g. communications modems shall have TX inputs and RX outputs on the left, TX outputs and RX inputs on the right.
  5. Simple IC symbols shall have inputs pins on the left.
  6. Simple IC symbols shall have power pins on the left.
    1. Positive power pins shall be at the top and double spaced above input pins.
    2. Negative power pins shall be at the bottom and double spaced below the input pins.
    3. GND pins shall be at the bottom and double spaced below the Negative power pins.
  7. Simple IC symbols shall have output pins on the right.
  8. Simple IC symbols shall have associated signals such as ‘DATA IN’ & ‘DATA OUT’ horizontally aligned with each other.
  9. Simple IC symbols shall have common function pins grouped together, for example DATA_IN, ENABLE and CLOCK on left and DATA_OUT opposite DATA_N on the right.
  10. Simple IC symbols shall have common function pin groups separated by a double pin space.
  11. Symbols for ICs with common multiple parts shall use multi-part symbols.
  12. Symbols for ICs with common multiple parts shall have power pins defined on part A.
  13. The designator shall be "U?" and shall be set as visible and placed at the top of the symbol.
  14. The comment field shall be set as not visible.
  15. There should be no parameters or Footprints for the schematic except the following two.
  16. A new parameter shall be added with the name "Value" and a value of "?" and be set as visible and placed at the bottom of the symbol.
  17. A second new parameter shall be added with the name "Footprint" and a value of "?" and be set as visible and placed below the previous parameter.