Vias are to be tented on the solder side with the exception of any associated with BGA devices which should be tented on the component side. Vias should not be tented on both sides as this runs the risk of trapping air / debris inside the barrel which could cause future reliability issues.

All PCB layers that carry switch path signals should be manufactured from 2oz copper; all other layers can be 1oz copper. Please note that it may be necessary to specify a non-switch layer as 2oz copper so that 2oz cores are paired together.

Routing of the coil drive lines should be for the best electrical performance and not attempt to match relay designator to serial loop bit order, for example RL1 does not need to connect to bit 0.

Components should not be present on the solder side unless absolutely necessary and even then the mechanical team should be consulted to ensure their height is suitable.

Copper pour / power plane connections to soldered components should be made using “thermal relief” connections unless a technical reason requires “direct connect”.

Copper pour / power plane connections to vias can be “direct connect”.

Copper pour / power plane connections to mechanical fixing points can be “direct connect”.

Regarding PCB rules, the standard practice is to have a set of “Design”  rules and another set of “Final” rules. Please note that the title of “Final” rules must remain unchanged but the actual clearances can be varied as necessary. The PCB should be designed using the “Design” rules and then the final step will be to switch to the “Final” rules and simply adjust their clearances to within 1 thou of failure, for example if a “Final” rule fails at 21 thou the rule should be set to 20 thou. The standard set of PCB rules is stored in the AtiumPickeringLib folder on the “Q:” drive server.

A clearance rule should be included that provides a 10 thou clearance from all drilled holes to any copper item i.e. trace, pour etc. This is in response to PCB fabricators capabilities changing and is to “catch” the clearance issue on pads that do not use the “simple” stack setting and have 0 thou diameter pads (typically on inner layers).

If there is an “FP_Ground” pin present on the front panel connector a wire link should be fitted to allow the pin to be isolated (space allowing). If a design is so dense to prevent the link from being fitted then a thermally relieved connection from the pin to “FP_Ground” is acceptable. The ability to remove the “FP_Ground” signal from the connector is required on PCBs used by Keysight and is included for potential future adoption of products by them.

For PCBs supplied in panels or requiring separation the slot dimensions should be defined to allow the use of depaneling tools. PCB fabricator should be advised of the following details:-

1. Slots in the waste area should be 2.4mm (this is the fabricators preferred cutter width) wide.
2. Slots in the waste area should be at least 16mm (tool minimum dimension, see image following) long.
3. The “pips” should be no bigger than 2.5mm (tool minimum dimension, see image following) long.

To contribute to achieving the highest possible voltage rating of the module it will be essential that certain design practices are followed. Problems have occurred historically when hot switching @ 300VDC caused data loop corruption and intermittent / unwanted operation of relays, the important points are as follows:-

1. Macroblock communication signals should ideally be on different layers than the switch path traces. If this is not possible then they should not “cross” switch path signals on other layers and should maintain a suitable clearance from any switch path traces or pads.
2. Place copper pours or power planes between the coil drive layer (normally solder side outer) and Macroblock comms signals if possible.
3. Switch path layers should have power planes either side of them to shield the comms lines.
4. Logic signals should not pass under relays even if a copper shielding plane is present.
5. Logic signals should be sandwiched between GND copper and not “FP_Ground” copper.
6. Areas of “FP_Ground” copper should not pass over areas of GND copper on other layers.
7. Copper pours connected to GND can be added to surround the Macroblock control signals.
8. Coil drive lines to be on the solder side outer layer where possible.